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FINAL
COM'L: -12/15/20
IND: -14/18/24
MACH110-12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
s 44 Pins s 32 Macrocells s 12 ns tPD Commercial 14 ns tPD Industrial s 77 MHz fCNT s 38 Inputs s 32 Outputs s 32 Flip-flops; 2 clock choices s 2 "PAL22V16" Blocks
Advanced Micro Devices
s Pin-compatible with MACH111, MACH210, MACH211, MACH215
GENERAL DESCRIPTION
The MACH110 is a member of AMD's high-performance EE CMOS MACH 1 family. This device has approximately three times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH110 consists of two PAL blocks interconnected by a programmable switch matrix. The two PAL blocks are essentially "PAL22V16" structures complete with product-term arrays and programmable macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH110 macrocell provides either registered or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input.
Publication# 14127 Rev. I Issue Date: May 1995
Amendment /0
AMD
BLOCK DIAGRAM
I/O0 - I/O15
I0 - I1, I3 - I4
16
16
I/O Cells 16 16 2
Macrocells
OE
44 x 70 AND Logic Array and Logic Allocator
4
22
Switch Matrix 22
44 x 70 AND Logic Array and Logic Allocator
OE
2
Macrocells 16 I/O Cells 16 16 16
2
2
I/O16 - I/O31
CLK1/I5, CLK0/I2
14127I-1
2
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CONNECTION DIAGRAM Top View PLCC
I/O31 I/O30 I/O29 I/O28 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 I/O14 I/O15 GND I/O18 I/O19 VCC I/O12 I/O13 I/O16 I/O17 I/O20
I/O0 GND 2
6 I/O5 I/O6 I/O7 I0 I1 GND CLK0/I2 I/O8 I/O9 I/O10 I/O11 7 8 9 10 11 12 13 14 15 16 17
5
I/O2 I/O1
4
3
1 44 43 42 41 40 I/O27 I/O26 I/O25 I/O24 CLK1/I5 GND I4 I3 I/O23 I/O22 I/O21
VCC
I/O4
I/O3
14127I-2
Note: Pin-compatible with MACH111, MACH210, MACH211, and MACH215.
PIN DESIGNATIONS
CLK/I = GND = I = I/O = VCC Clock or Input Ground Input Input/Output
= Supply Voltage
MACH110-12/15/20
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AMD
ORDERING INFORMATION Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
MACH
110 -12
J
C
FAMILY TYPE MACH = Macro Array CMOS High-Speed
OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial (0C to +70C)
DEVICE NUMBER 110 = 32 Macrocells, 44 Pins SPEED -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD
PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044)
Valid Combinations MACH110-12 MACH110-15 MACH110-20 JC
Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
4
MACH110-12/15/20 (Com'l)
AMD
ORDERING INFORMATION Industrial Products
AMD programmable logic products for Industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
MACH
110
-14
J
I
FAMILY TYPE MACH = Macro Array CMOS High-Speed DEVICE NUMBER 110 = 32 Macrocells, 44 Pins SPEED -14 = 14 ns tPD -18 = 18 ns tPD -24 = 24 ns tPD
OPTIONAL PROCESSING Blank = Standard Processing
OPERATING CONDITIONS I = Industrial (-40C to +85C) PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044)
Valid Combinations MACH110-14 MACH110-18 MACH110-24 JI
Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
MACH110-14/18/25 (Ind)
5
AMD
FUNCTIONAL DESCRIPTION
The MACH110 consists of two PAL blocks connected by a switch matrix. There are 32 I/O pins and 6 dedicated input pins feeding the switch matrix. These signals are distributed to the two PAL blocks for efficient design implementation. There are two clock pins that can also be used as dedicated inputs.
Table 1. Logic Allocation
Output Macrocell M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 Available Clusters C0, C1 C0, C1, C2 C1, C2, C3 C2, C3, C4 C3, C4, C5 C4, C5, C6 C5, C6, C7 C6, C7 C8, C9 C8, C9, C10 C9, C10, C11 C10, C11, C12 C11, C12, C13 C12, C13, C14 C13, C14, C15 C14, C15
The PAL Blocks
Each PAL block in the MACH110 (Figure 1) contains a 64-product-term logic array, a logic allocator, 16 macrocells and 16 I/O cells. The switch matrix feeds each PAL block with 22 inputs. This makes the PAL block look effectively like an independent "PAL22V16". There are four additional output enable product terms in each PAL block. For purposes of output enable, the 16 I/O cells are divided into 2 banks of 8 macrocells. Each bank is allocated two of the output enable product terms. An asynchronous reset product term and an asynchronous preset product term are provided for flip-flop initialization. All flip-flops within the PAL block are initialized together.
The Macrocell
The MACH110 macrocells can be configured as either registered or combinatorial, with programmable polarity. The macrocell provides internal feedback whether configured as registered or combinatorial. The flip-flops can be configured as D-type or T-type, allowing for product-term optimization. The flip-flops can individually select one of two clock pins, which are also available as data inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The flip-flops can also be asynchronously initialized with the common asynchronous reset and preset product terms.
The Switch Matrix
The MACH110 switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each PAL block provides 16 internal feedback signals and 16 I/O feedback signals. The switch matrix distributes these signals back to the PAL blocks in an efficient manner that also provides for high performance. The design software automatically configures the switch matrix when fitting a design into the device.
The Product-Term Array
The MACH110 product-term array consists of 64 product terms for logic use, and 6 special-purpose product terms. Four of the special-purpose product terms provide programmable output enable, one provides asynchronous reset, and one provides a synchronous preset. Two of the output enable product terms are used for the first eight I/O cells; the other two control the last eight macrocells.
The I/O Cell
The I/O cell in the MACH110 consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to eight I/O cells. Within each PAL block, two product terms are available for selection by the first eight three-state outputs; two other product terms are available for selection by the last eight three-state outputs. These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus.
The Logic Allocator
The logic allocator in the MACH110 takes the 64 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven by up to 12 product terms. The design software automatically configures the logic allocator when fitting the design into the device. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers. 6
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0 4 8 12 16 20 24 28 32 36 40 43 Output Enable Output Enable Asynchronous Reset Asynchronous Preset
M0
Output Macro Cell
I/O Cell
I/O
M1
Output Macro Cell
I/O Cell
I/O
M2
Output Macro Cell
I/O Cell
I/O
M3
0
Output Macro Cell
I/O Cell
I/O
C0 C1 C2 C3 C4 C5 Logic Allocator
I/O Cell
M4
Output Macro Cell
I/O
M5
Output Macro Cell
I/O Cell
I/O
I/O Cell
I/O
M6
Output Macro Cell
Switch Matrix
C6 C7 C8 C9
I/O Cell
I/O
M7
Output Macro Cell
M8
Output Macro Cell
I/O Cell
I/O
C10 C11 C12 C13 C14 C15
63
M9
Output Macro Cell
I/O Cell
I/O
M10
Output Macro Cell
I/O Cell
I/O
M11
Output Macro Cell
I/O Cell
I/O
M12
Output Macro Cell
I/O Cell
I/O
I/O Cell
I/O
M13
Output Macro Cell
I/O Cell Output Macro Cell I/O Cell Output Macro Cell
I/O
M14
I/O
M15
CLK 4 Output Enable Output Enable 0 4 8 16 16 12 16 20 24 28 32 36 40 43
14127I-3
Figure 1. MACH110 PAL Block
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AMD
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature With Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to 70C) . . . . . . . . . . . . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current (Typical) Test Conditions IOH = -3.2 mA, VCC = Min VIN = VIH or VIL IOL = 16 mA, VCC = Min VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = 5 V, TA=25C, f = 25 MHz (Note 4) -30 95 2.0 0.8 10 -10 10 -10 -160 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter program. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.
8
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CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V, TA = 25C f = 1 MHz Typ 6 8 Unit pF pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter Symbol Parameter Description tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) Setup Time from Input, I/O, or Feedback to Clock Hold Time Clock to Output (Note 3) Clock Width LOW HIGH D-type External Feedback 1/(tS + tCO) fMAX Maximum Frequency (Note 1) Internal Feedback (fCNT) No Feedback tAR tARW tARR tAP tAPW tAPR tEA tER 1/(tWL + tWH) T-type D-type T-type 6 6 66.7 62.5 76.9 71.4 83.3 16 12 8 16 12 8 12 12 15 10 15 15 15 10 20 20 15 20 20 D-type T-type 7 8 0 8 6 6 50 47.6 66.6 55.5 83.3 20 20 15 25 Min -12 Max 12 10 11 0 10 8 8 40 38.5 47.6 43.5 62.5 25 -15 Min Max 15 13 14 0 12 -20 Min Max 20 Unit ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns
tS tH tCO tWL tWH
Asynchronous Reset to Registered Output Asynchronous Reset Width (Note 1) Asynchronous Reset Recovery Time (Note 1) Asynchronous Preset to Registered Output Asynchronous Preset Width (Note 1) Asynchronous Preset Recovery Time (Note 1) Input, I/O, or Feedback to Output Enable (Note 3) Input, I/O, or Feedback to Output Disable (Note 3)
Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching.
MACH110-12/15/20 (Com'l)
9
AMD
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature With Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40C to +85C) . . . . . . . . . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
INDUSTRIAL OPERATING RANGES
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . -40C to +85C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current (Typical) Test Conditions IOH = -3.2 mA, VCC = Min VIN = VIH or VIL IOL = 16 mA, VCC = Min VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT= 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = 5 V, TA = 25C, f = 25 MHz (Note 4) -30 95 2.0 0.8 10 -10 10 -10 -160 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH ). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.
10
MACH110-14/18/20 (Ind)
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CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V, TA = 25C f = 1 MHz Typ 6 8 Unit pF pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter Symbol Parameter Description tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) Setup Time from Input, I/O, or Feedback to Clock Hold Time Clock to Output (Note 3) Clock Width LOW HIGH D-type External Feedback 1/(tS + tCO) fMAX Maximum Frequency (Note 1) Internal Feedback (fCNT ) No Feedback tAR tARW tARR tAP tAPW tAPR tEA tER 1/(tWL + tWH) T-type D-type T-type 7.5 7.5 53.5 50 61.5 57 66.5 19.5 14.5 10 19.5 14.5 10 14.5 14.5 18 12 18 18 18 12 24 24 18 24 24 D-type T-type 8.5 10 0 10 7.5 7.5 40 38 53 44 66.5 24 24 18 30 Min -14 Max 14.5 12 13.5 0 12 10 10 32 30 38 34.5 50 30 -18 Min Max 18 16 17 0 14.5 -24 Min Max 24 Unit ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns
tS tH tCO tWL tWH
Asynchronous Reset to Registered Output Asynchronous Reset Width (Note 1) Asynchronous Reset Recovery Time (Note 1) Asynchronous Preset to Registered Output Asynchronous Preset Width (Note 1) Asynchronous Preset Recovery Time (Note 1) Input, I/O, or Feedback to Output Enable (Note 3) Input, I/O, or Feedback to Output Disable (Note 3)
Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching.
MACH110-14/18/20 (Ind)
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AMD
TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS
VCC = 5.0 V, TA = 25C
IOL (mA) 80 60 40 20 VOL (V) -1.0 -0.8 -0.6 -0.4 -0.2 -20 -40 -60 -80 .2 .4 .6 .8 1.0
Output, LOW
IOH (mA) 25 1 -3 -2 -1 -25 -50 -75 -100 -125 -150 2 3 4 5 VOH (V)
14127I-4
14127I-5
Output, HIGH II (mA)
20
VI (V)
-2 -1 -20 -40 -60 -80 -100
14127I-6
1
2
3
4
5
Input 12 MACH110-12/15/20
AMD
TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25C
150
125 MACH110
100
ICC (mA)
75
50
25
0 0 10 20 30 40 50 60 70 80 90
14127I-7
Frequency (MHz)
The selected "typical" pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register.
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TYPICAL THERMAL CHARACTERISTICS
Measured at 25C ambient. These parameters are not tested.
Parameter Symbol jc ja jma Parameter Description Thermal impedance, junction to case Thermal impedance, junction to ambient Thermal impedance, junction to ambient with air flow 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air Typ PLCC 14 39 33 30 27 25 Unit C/W C/W C/W C/W C/W C/W
Plastic jc Considerations
The data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment.
14
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SWITCHING WAVEFORMS
Input, I/O, or Feedback
VT tPD
Combinatorial Output
VT
14127I-8
Combinatorial Output
Input, I/O, or Feedback tS Clock VT tCO Registered Output
VT tH
Input, I/O, or Feedback tSL Gate tPDL VT
14127I-9
VT tHL VT tGO VT
14127I-10
Latched Out
Registered Output
Latched Output (MACH 2, 3, and 4)
tWH Clock tWL
14127I-11
Gate tGWS
VT
14127I-12
Clock Width
Gate Width (MACH 2, 3, and 4)
Registered Input tSIR Input Register Clock Combinatorial Output VT tICO
VT tHIR
Registered Input Input Register Clock VT Output Register Clock
VT
VT
tICS
VT
14127I-14
14127I-13
Registered Input (MACH 2 and 4)
Input Register to Output Register Setup (MACH 2 and 4)
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
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SWITCHING WAVEFORMS
Latched In tSIL Gate
VT tHIL VT tIGO
Combinatorial Output
VT
14127I-15
Latched Input (MACH 2 and 4)
tPDLL Latched In Latched Out Input Latch Gate tIGOL VT
VT
tIGS Output Latch Gate
tSLL VT
14127I-16
Latched Input and Output (MACH 2, 3, and 4)
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
16
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SWITCHING WAVEFORMS
tWICH Clock tWICL
14127I-17
VT
Input Latch Gate tWIGL
VT
14127I-18
Input Register Clock Width (MACH 2 and 4)
Input Latch Gate Width (MACH 2 and 4)
tARW Input, I/O, or Feedback tAR Registered Output VT tARR Clock VT
14127I-19
tAPW VT Input, I/O, or Feedback tAP Registered Output VT tAPR Clock VT
14127I-20
VT
Asynchronous Reset
Asynchronous Preset
Input, I/O, or Feedback tER Outputs VOH - 0.5V VOL + 0.5V
VT tEA VT
14127I-21
Output Disable/Enable
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
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AMD
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
5V
S1
R1 Output R2 Test Point
CL
14127I-22
Commercial Specification tPD, tCO tEA tER S1 Closed Z H: Open Z L: Closed H Z: Open L Z: Closed 35 pF 300 5 pF 390 CL R1 R2
Measured Output Value 1.5 V 1.5 V H Z: VOH - 0.5 V L Z: VOL + 0.5 V
*Switching several outputs simultaneously should be avoided for accurate measurement.
18
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fMAX PARAMETERS
The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated "fMAX external." The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is designated "fMAX internal". A simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called "fCNT." The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated "fMAX no feedback." For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same path, the overall frequency will be limited by tICS. All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is measured directly.
CLK
CLK
(SECOND CHIP) LOGIC REGISTER LOGIC REGISTER
tS
t CO fMAX External; 1/(tS + tCO) CLK
tS
fMAX Internal (fCNT) CLK
LOGIC
REGISTER
REGISTER
LOGIC
tS
tSIR
tHIR fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)
14127I-23
fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL)
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ENDURANCE CHARACTERISTICS
The MACH families are manufactured using AMD's advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory.
Endurance Characteristics
Parameter Symbol Parameter Description Min 10 tDR N Min Pattern Data Retention Time Max Reprogramming Cycles 20 100 Units Years Years Cycles Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions
20
MACH110-12/15/20
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INPUT/OUTPUT EQUIVALENT SCHEMATICS
VCC
100 k 1 k VCC
ESD Protection
Input
VCC
VCC
100 k
1 k
Preload Circuitry
Feedback Input
14127I-24
I/O
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AMD
POWER-UP RESET
The MACH devices have been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the
Parameter Symbol tPR tS tWL
wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met.
Parameter Descriptions Power-Up Reset Time Input or Feedback Setup Time Clock Width LOW
Max 10 See Switching Characteristics
Unit s
VCC
Power 4V
tPR
Registered Output
tS
Clock
tWL
14127I-25
Power-Up Reset Waveform
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USING PRELOAD AND OBSERVABILITY
In order to be testable, a circuit must be both controllable and observable. To achieve this, the MACH devices incorporate register preload and observability. In preload mode, each flip-flop in the MACH device can be loaded from the I/O pins, in order to perform functional testing of complex state machines. Register preload makes it possible to run a series of tests from a known starting state, or to load illegal states and test for proper recovery. This ability to control the MACH device's internal state can shorten test sequences, since it is easier to reach the state of interest. The observability function makes it possible to see the internal state of the buried registers during test by overriding each register's output enable and activating the output buffer. The values stored in output and buried registers can then be observed on the I/O pins. Without this feature, a thorough functional test would be impossible for any designs with buried registers. While the implementation of the testability features is fairly straightforward, care must be taken in certain instances to insure valid testing. One case involves asynchronous reset and preset. If the MACH registers drive asynchronous reset or preset lines and are preloaded in such a way that reset or preset are asserted, the reset or preset may remove the preloaded data. This is illustrated in Figure 2. Care should be taken when planning functional tests, so that states that will cause unexpected resets and presets are not preloaded. Another case to be aware of arises in testing combinatorial logic. When an output is configured as combinatorial, the observability feature forces the output into registered mode. When this happens, all product terms are forced to zero, which eliminates all combinatorial data. For a straight combinatorial output, the correct value will be restored after the preload or observe function, and there will be no problem. If the function implements a combinatorial latch, however, it relies on feedback to hold the correct value, as shown in Figure 3. As this value may change during the preload or observe operation, you cannot count on the data being correct after the operation. To insure valid testing in these cases, outputs that are combinatorial latches should not be tested immediately following a preload or observe sequence, but should first be restored to a known state. All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support.
Reset Figure 3. Combinatorial Latch
14127I-27
Preloaded HIGH D Q1
Q
AR
Preloaded HIGH D Q2
Q
AR
On Preload Mode Off
Q1
AR
Q2
Figure 2. Preload/Reset Conflict
14127I-26
Set
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AMD
DEVELOPMENT SYSTEMS (subject to change) For more information on the products listed below, please consult the AMD FusionPLD Catalog.
MANUFACTURER
Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Cadence Design Systems 555 River Oaks Pkwy San Jose, CA 95134 (408) 943-1234 Capilano Computing 960 Quayside Dr., Suite 406 New Westminster, B.C. Canada V3M 6G2 (800) 444-9064 or (604) 552-6200 CINA, Inc. P.O. Box 4872 Mountain View, CA 94040 (415) 940-1723 Data I/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 iNt GmbH Busenstrasse 6 D-8033 Martinsried, Munich, Germany (89) 857-6667 ISDATA GmbH Daimlerstr. 51 D7500 Karlsruhe 21 Germany Germany: 0721/75 10 87 U.S.: (510) 531-8553 Logic Modeling 19500 NW Gibbs Dr. P.O. Box 310 Beaverton, OR 97075 (503) 690-6900 Logical Devices, Inc. 692 S. Military Trail Deerfield Beach, FL 33442 (800) 331-7766 or (305) 428-6868
SOFTWARE DEVELOPMENT SYSTEMS
MACHXL(R) Software Ver. 2.0
Design Center/AMD Software
AMD-ABEL Software Data I/O MACH Fitters
PROdeveloper/AMD Software PROsynthesis/AMD Software ComposerPICTM Designer (Requires MACH Fitter) Verilog, LeapFrog, RapidSim Simulators (Models also available from Logic Modeling) Ver. 3.3
MacABELTM Software (Requires SmartPart MACH Fitter)
SmartCAT Circuit Analyzer
ABELTM-5 Software (Requires MACH Fitter) SynarioTM Software
PLDSim 90
LOG/iCTM Software (Requires MACH Fitter)
SmartModel(R) Library
CUPLTM Software
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DEVELOPMENT SYSTEMS (subject to change) (continued)
MANUFACTURER
Mentor Graphics Corp. 8005 S.W. Boeckman Rd. Wilsonville, OR 97070-7777 (800) 547-3000 or (503) 685-7000 MicroSim Corp. 20 Fairbanks Irvine, CA 92718 (714) 770-3022 MINC Incorporated 6755 Earl Drive, Suite 200 Colorado Springs, CO 80918 (800) 755-FPGA or (719) 590-1155 OrCAD 3175 N.W. Aloclek Dr. Hillsboro, OR 97124 (503) 690-9881 SUSIE-CAD 10000 Nevada Highway, Suite 201 Boulder City, NV 89005 (702) 293-2271 Teradyne EDA 321 Harrison Ave. Boston, MA 02118 (800) 777-2432 or (617) 422-2793 Viewlogic Systems, Inc. 293 Boston Post Road West Marlboro, MA 01752 (800) 442-4660 or (508) 480-0881
SOFTWARE DEVELOPMENT SYSTEMS
PLDSynthesisTM (Requires MACH Fitter) QuickSim Simulator (Models also available from Logic Modeling)
Design Center Software (Requires MACH Fitter)
PLDesignerTM-XL Software (Requires MACH Fitter)
Programmable Logic Design Tools 386+ Schematic Design Tool 386+ Digital Simulation Tools
SUSIETM Simulator
MultiSIM Interactive Simulator LASAR
ViewPLD or PROPLD (Requires PROSim Simulator MACH Fitter) ViewSim Simulator (Models for ViewSim also available from Logic Modeling)
MANUFACTURER
Acugen Software, Inc. 427-3 Amherst St., Suite 391 Nashua, NH 03063 (603) 891-1995 iNt GmbH Busenstrasse 6 D-8033 Martinsried, Munich, Germany (87) 857-6667
TEST GENERATION SYSTEM
ATGENTM Test Generation Software
PLDCheck 90
Advanced Micro Devices is not responsible for any information relating to the products of third parties. The inclusion of such information is not a representation nor an endorsement by AMD of these products.
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AMD
APPROVED PROGRAMMERS (subject to change)
For more information on the products listed below, please consult the AMD FusionPLD Catalog.
MANUFACTURER
Advin Systems, Inc. 1050-L East Duane Ave. Sunnyvale, CA 94086 (408) 243-7000 BP Microsystems 100 N. Post Oak Rd. Houston, TX 77055-7237 (800) 225-2102 or (713) 688-4600 Data I/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 Logical Devices Inc./Digelec 692 S. Military Trail Deerfield Beach, FL 33442 (800) 331-7766 or (305) 428-6868 SMS North America, Inc. 16522 NE 135th Place Redmond, WA 98052 (800) 722-4122 or SMS lm Grund 15 D-7988 Vangen Im Allgau, Germany 07522-5018 Stag Microsystems Inc. 1600 Wyatt Dr. Suite 3 Santa Clara, CA 95054 (408) 988-1118 or Stag House Martinfield, Welwyn Garden City Herfordshire UK AL7 1JT 707-332148 System General 510 S. Park Victoria Dr. Milpitas, CA 95035 (408) 263-6667 or 3F, No. 1, Alley 8, Lane 45 Bao Shing Rd., Shin Diau Taipei, Taiwan 2-917-3005
PROGRAMMER CONFIGURATION
Pilot U84
BP1200
UniSiteTM
Model 3900
AutoSite
ALLPROTM-88
Sprint/Expert
Stag Quazar
Turpro-1
APPROVED ON-BOARD PROGRAMMERS
MANUFACTURER
Corelis, Inc. 12607 Hidden Creek Way, Suite H Cerritos, California 70703 (310) 926-6727 Advanced Micro Devices P.O. Box 3453, MS-1028 Sunnyvale, CA 94088-3453 (800) 222-9323
PROGRAMMER CONFIGURATION
JTAG PROG
MACHpro
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PROGRAMMER SOCKET ADAPTERS (subject to change)
MANUFACTURER
EDI Corporation P.O. Box 366 Patterson, CA 95363 (209) 892-3270 Emulation Technology 2344 Walsh Ave., Bldg. F Santa Clara, CA 95051 (408) 982-0660 Logical Systems Corp. P.O. Box 6184 Syracuse, NY 13217-6184 (315) 478-0722 Procon Technologies, Inc. 1333 Lawrence Expwy, Suite 207 Santa Clara, CA 95051 (408) 246-4456
PART NUMBER
Contact Manufacturer
Contact Manufacturer
Contact Manufacturer
Contact Manufacturer
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AMD
PHYSICAL DIMENSIONS* PL 044 44-Pin Plastic Leaded Chip Carrier (measured in inches)
.685 .695
.650 .656
.042 .056
.062 .083
Pin 1 I.D. .685 .695 .650 .656 .500 .590 REF .630
.013 .021
.026 .032
.050 REF
.009 .015
.090 .120 .165 .180
SEATING PLANE
TOP VIEW
SIDE VIEW
16-038-SQ PL 044 DA78 6-28-94 ae
*For reference only. BSC is an ANSI standard for Basic Space Centering.
Trademarks Copyright (c) 1995 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, MACH, and PAL are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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